Intel® Technology Journal

45nm Design for Manufacturing

Sat, 09 Aug 2008 02:15:53 -0400

Co-optimization between design and process has lead to changes in design rules for the last few process generations, especially changes in Poly, one of the most critical layers for control of variation. The variation, density, and yields on the 45nm process validate these Intel engineers' Design for Manufacturing methodology.

45nm SRAM Technology Development and Technology Lead Vehicle

Sat, 09 Aug 2008 02:15:53 -0400

The authors look at the X-chip and its role in enabling process development for the 45nm node. The SRAM design challenges due to scaling and circuit innovations are discussed along with the advantages provided by Hi-K metal gate technology in achieving aggressive design goals.

Managing Process Variation in Intel's 45nm CMOS Technology

Wed, 06 Aug 2008 02:16:30 -0400

The key message of this paper is that process variation is not an insurmountable barrier to Moore's Law. The authors use data from the 45nm process generation where process variation is shown to be at least equivalent to (and in many cases better than) process variation in the 65nm- and 90nm-process generations.

Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation

Mon, 14 Jul 2008 03:21:36 -0400

Here, the authors explore the issues associated with on-die interconnects and describe how they are addressed on Intel's 45nm high-performance logic process technology. The combined MT1-MT9 interconnect stack provides high performance and high reliability, and enables a completely Pb-free product.

Preface

Sat, 05 Jul 2008 03:23:26 -0400

Hello. This Q2'08 Intel Technology Journal (Vol. 12, Issue 2) covers Intel's 45nm CMOS technology which proved pivotal to the advancement in silicon processes technology by extending Moore's Law.

Podcast with Kaizad Mistry, VP Technology & Manufacturing Group, Intel

Sat, 28 Jun 2008 03:24:51 -0400

Podcast with Kaizad Mistry, VP Technology & Manufacturing Group, Intel

Foreword

Sat, 28 Jun 2008 03:24:51 -0400

Bill Holt, Senior Vice President, General Manager, Technology and Manufacturing Group

45nm High-k+Metal Gate Strain-Enhanced Transistors

Tue, 17 Jun 2008 03:27:05 -0400

In this paper, the authors detail the transistors used in Intel's 45nm technology node that feature high-k gate dielectrics and metal gates along with a third generation of strained silicon to achieve record NMOS and PMOS performance.

Preface

Sat, 23 Feb 2008 03:42:35 -0500

Intel Corporations four-decade history of technology innovations is a well-known fact. Less known but equally important is that for decades Intel has had goals to reduce the environmental impact of its manufacturing, operations, and products. This issue of the Intel Technology Journal on Eco-Smart Technologies (Volume 12, Issue 1, 2008) features a podcast by Ted Reichelt, Intels Principal Environmental Engineer, as he remembers operational meetings with Gordon Moore and Andy Grove held nearly two decades ago on this very subject. Today, Intels commitment to design for environment remains strong: our goal is to reduce the environmental impact of our operations while continuing to meet high-performance requirements for computing.

Materials Technology for Environmentally Green Micro-electronic Packaging

Thu, 21 Feb 2008 03:42:58 -0500

Learn how the delivery of lead-free packaging solutions reinforced Intels commitment to provide environmentally friendly micro-electronic packaging.

Process Scheduling Challenges in the Era of Multi-Core Processors

Sat, 26 Jan 2008 03:48:15 -0500

These authors examine a critical component of system software, the process scheduler, in todays multi-core environment. They show how optimal performance can be exploited by making the process scheduler aware of the multi-core topologies and task characteristics.

Accelerating Video Feature Extractions in CBVIR on Multi-Core Systems

Sat, 19 Jan 2008 03:49:40 -0500

Todays user-friendly and abundant video capture and storage techniques have resulted in an explosion of video data that needs to be managed. Our authors show how Content-Based Video Information Retrieval (CBVIR) can be accelerated to take full advantage of todays multi-core systems.

Future-Proof Data Parallel Algorithms and Software on Intel® Multi-Core Architecture

Sat, 12 Jan 2008 03:51:04 -0500

This paper highlights the Ct API, a programming model that leverages the strengths of data parallel programming. The authors show how this API is an effective way to create scalable, future-proof applications without seriously compromising the language design or the large software investment by developers.

Methodology, Tools, and Techniques to Parallelize Large-Scale Applications: A Case Study

Sat, 05 Jan 2008 03:52:29 -0500

These authors show you how advancements in threading analysis tools have made parallelization of large and complex applications an easier task than what it was a decade or two ago. They showcase their successful threading of the Intel® C++ Compiler which produced an average speedup of 2x in compiling a range of CPU2000 benchmarks.

The Foundations for Scalable Multi-Core Software in Intel® Threading Building Blocks

Mon, 31 Dec 2007 03:53:34 -0500

The Intel® Threading Building Blocks (Intel® TBB) are a template library designed to raise the level of abstraction for parallelism as developers port their code to multi-core platforms. Learn about its work-stealing task scheduler and scalable memory allocator, the basics of TBBs robust performance and scalability.